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构建数字通信技术理论与实践之间的桥梁

孤云出岫去留一无所系 朗镜悬空静躁两不相干 菜根谭.明.洪应明

 
 
 

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《数字通信同步技术的MTALAB与FPGA实现》-目录  

2014-07-25 13:34:36|  分类: 通信同步技术 |  标签: |举报 |字号 订阅

  下载LOFTER 我的照片书  |

 目录

 

第1章  同步技术的概念及FPGA基础······································································································· 1

1.1  数字通信中的同步技术······························································································································ 2

1.2  同步技术的实现方法·································································································································· 4

1.2.1  两种不同的实现原理······················································································································ 4

1.2.2  常用的工程实现途径······················································································································ 5

1.3  FPGA概念及其在信号处理中的应用······································································································ 6

1.3.1  基本概念及发展历程······················································································································ 6

1.3.2  FPGA的结构和工作原理·············································································································· 8

1.3.3  FPGA在数字信号处理中的应用································································································ 14

1.4  Xilinx器件简介········································································································································· 15

1.4.1  Xilinx器件概况····························································································································· 15

1.4.2  Spartan系列器件··························································································································· 17

1.4.3  Virtex系列器件····························································································································· 18

1.5  设计语言及环境简介································································································································ 19

1.5.1  VHDL语言···································································································································· 19

1.5.2  ISE环境及综合仿真工具············································································································· 22

1.5.3  FPGA设计流程···························································································································· 28

1.5.4  MATLAB软件····························································································································· 31

1.5.5  MATLAB与ISE的数据交互······································································································ 34

1.6  小结···························································································································································· 35

第2章  FPGA实现数字信号处理基础······································································································ 37

2.1  FPGA中数的表示···································································································································· 38

2.1.1  莱布尼兹与二进制························································································································ 38

2.1.2  定点数表示···································································································································· 39

2.1.3  浮点数表示···································································································································· 40

2.2  FPGA中数的运算···································································································································· 43

2.2.1  加/减法运算··································································································································· 43

2.2.2  乘法运算········································································································································ 46

2.2.3  除法运算········································································································································ 48

2.2.4  有效数据位的计算························································································································ 49

2.3  有限字长效应············································································································································ 51

2.3.1  字长效应的产生因素···················································································································· 51

2.3.2  A/D变换的字长效应···················································································································· 52

2.3.3  系统运算中的字长效应················································································································ 53

2.4  FPGA中的常用处理模块························································································································ 55

2.4.1  乘法器模块···································································································································· 55

2.4.2  除法器模块···································································································································· 60

2.4.3  浮点运算模块································································································································ 62

2.4.4  滤波器模块···································································································································· 64

2.4.5  数字频率器模块···························································································································· 67

2.5  小结···························································································································································· 68

第3章  锁相技术原理及应用························································································································· 71

3.1  锁相环的工作原理···································································································································· 72

3.1.1  锁相环路的模型···························································································································· 72

3.1.2  锁定与跟踪的概念························································································································ 73

3.1.3  环路的基本性能要求···················································································································· 74

3.2  锁相环的组成············································································································································ 75

3.2.1  鉴相器············································································································································ 75

3.2.2  环路滤波器···································································································································· 76

3.2.3  压控振荡器···································································································································· 77

3.3  锁相环路的动态方程································································································································ 77

3.3.1  非线性相位模型···························································································································· 77

3.3.2  线性相位模型································································································································ 79

3.3.3  环路的传递函数···························································································································· 80

3.4  锁相环路的性能分析································································································································ 82

3.4.1  暂态信号响应································································································································ 82

3.4.2  环路的频率响应···························································································································· 84

3.4.3  环路的稳定性································································································································ 86

3.4.4  非线性跟踪性能···························································································································· 87

3.4.5  环路的捕获性能···························································································································· 89

3.4.6  环路的噪声性能···························································································································· 90

3.5  锁相环路的应用········································································································································ 92

3.5.1  环路的两种跟踪状态···················································································································· 92

3.5.2  调频解调器···································································································································· 93

3.5.3  调相解调器···································································································································· 94

3.5.4  调幅信号的相干解调···················································································································· 94

3.5.5  锁相调频器···································································································································· 95

3.5.6  锁相调相器···································································································································· 95

3.6  小结···························································································································································· 96

第4章  载波同步的FPGA实现··················································································································· 97

4.1  载波同步的原理········································································································································ 98

4.1.1  载波同步的概念及实现方法········································································································ 98

4.1.2  锁相环的工作方式························································································································ 99

4.2  锁相环路的数字化模型·························································································································· 100

4.2.1  数字鉴相器·································································································································· 100

4.2.2  数字环路滤波器·························································································································· 101

4.2.3  数字控制振荡器·························································································································· 102

4.2.4  数字环路的动态方程·················································································································· 103

4.3  输入信号建模与仿真······························································································································ 104

4.3.1  工程实例需求······························································································································ 104

4.3.2  输入信号模型······························································································································ 105

4.3.3  输入信号的MATLAB仿真······································································································ 107

4.4  载波同步环的参数设计·························································································································· 109

4.4.1  总体性能参数设计······················································································································ 110

4.4.2  数字鉴相器设计·························································································································· 111

4.4.3  环路滤波器及数控振荡器设计·································································································· 114

4.5  载波同步环的FPGA实现····················································································································· 116

4.5.1  顶层模块的VHDL实现············································································································· 116

4.5.2  IIR低通滤波器的VHDL实现··································································································· 119

4.5.3  环路滤波器的VHDL实现········································································································· 123

4.5.4  同步环路的FPGA实现············································································································· 125

4.6  载波同步环的仿真测试·························································································································· 126

4.6.1  测试激励的VHDL设计············································································································· 126

4.6.2  单载波输入信号的仿真测试······································································································ 129

4.6.3  调幅波输入信号的仿真测试······································································································ 133

4.6.4  关于载波环路参数的讨论·········································································································· 136

4.7  小结·························································································································································· 138

第5章  抑制载波同步的FPGA实现········································································································ 139

5.1  抑制载波同步的原理······························································································································ 140

5.1.1  平方环工作原理························································································································ 140

5.1.2  同相正交环工作原理················································································································ 141

5.1.3  判决反馈环工作原理················································································································ 142

5.2  输入信号建模与仿真······························································································································ 144

5.2.1  工程实例需求···························································································································· 144

5.2.2  DPSK调制原理及信号特征····································································································· 144

5.2.3  DPSK信号传输模型及仿真····································································································· 145

5.3  平方环的FPGA实现····························································································································· 147

5.3.1  改进的平方环原理···················································································································· 147

5.3.2  环路性能参数设计···················································································································· 148

5.3.3  带通滤波器设计························································································································ 149

5.3.4  顶层模块的VHDL实现··········································································································· 151

5.3.5  带通滤波器的VHDL实现······································································································· 155

5.3.6  其他模块的VHDL实现··········································································································· 159

5.3.7  FPGA实现后的仿真测试········································································································· 160

5.4  同相正交环的FPGA实现····················································································································· 162

5.4.1  环路性能参数设计···················································································································· 162

5.4.2  低通滤波器VHDL实现··········································································································· 163

5.4.3  其他模块的VHDL实现··········································································································· 165

5.4.4  顶层模块的VHDL实现··········································································································· 165

5.4.5  FPGA实现后的仿真测试········································································································· 168

5.4.6  同相支路的判决及码型变换···································································································· 169

5.5  判决反馈环的FPGA实现····················································································································· 171

5.5.1  环路性能参数设计···················································································································· 171

5.5.2  顶层模块的VHDL实现··········································································································· 172

5.5.3  积分判决模块的VHDL实现··································································································· 176

5.5.4  FPGA实现后的仿真测试········································································································· 178

5.6  小结·························································································································································· 179

第6章  自动频率控制的FPGA实现········································································································ 181

6.1  自动频率控制的概念······························································································································ 182

6.2  最大似然频偏估计的FPGA实现········································································································· 183

6.2.1  最大似然频偏估计的原理········································································································ 183

6.2.2  最大似然频偏估计的MATLAB仿真····················································································· 185

6.2.3  频偏估计的FPGA实现方法···································································································· 187

6.2.4  CORDIC核的使用···················································································································· 189

6.2.5  顶层文件的VHDL实现··········································································································· 192

6.2.6  频偏估计模块的VHDL实现··································································································· 195

6.2.7  FPGA实现及仿真测试············································································································· 198

6.3  基于FFT载频估计的FPGA实现········································································································ 200

6.3.1  离散傅里叶变换························································································································ 200

6.3.2  FFT算法原理及MATLAB仿真···························································································· 202

6.3.3  FFT核的使用···························································································································· 204

6.3.4  输入信号建模与MATLAB仿真····························································································· 207

6.3.5  基于FFT载频估计的VHDL实现·························································································· 208

6.3.6  FPGA实现及仿真测试············································································································· 211

6.4  FSK信号调制解调原理························································································································· 212

6.4.1  数字频率调制···························································································································· 213

6.4.2  FSK信号的MATLAB仿真···································································································· 214

6.4.3  FSK相干解调原理···················································································································· 217

6.4.4  AFC环解调FSK信号的原理·································································································· 218

6.5  AFC环的FPGA实现···························································································································· 220

6.5.1  环路参数设计···························································································································· 220

6.5.2  顶层模块的VHDL实现··········································································································· 222

6.5.3  鉴频器模块的VHDL实现······································································································· 225

6.5.4  FPGA实现及仿真测试············································································································· 226

6.6  小结·························································································································································· 227

第7章  位同步技术的FPGA实现············································································································· 229

7.1  位同步的概念及实现方法······················································································································ 230

7.1.1  位同步的概念···························································································································· 230

7.1.2  滤波法提取位同步···················································································································· 231

7.1.3  数字锁相环位同步法················································································································ 232

7.2  微分型位同步的FPGA实现················································································································· 234

7.2.1  微分型位同步的原理················································································································ 234

7.2.2  顶层模块的VHDL实现··········································································································· 235

7.2.3  双相时钟信号的VHDL实现··································································································· 238

7.2.4  微分鉴相模块的VHDL实现··································································································· 240

7.2.5  单稳触发器的VHDL实现······································································································· 241

7.2.6  控制及分频模块的VHDL实现······························································································· 243

7.2.7  位同步形成及移相模块的VHDL实现··················································································· 244

7.2.8  FPGA实现及仿真测试············································································································· 246

7.3  积分型位同步的FPGA实现················································································································· 248

7.3.1  积分型位同步的原理················································································································ 248

7.3.2  顶层模块的VHDL实现··········································································································· 250

7.3.3  积分模块的VHDL实现··········································································································· 254

7.3.4  鉴相模块的VHDL实现··········································································································· 255

7.3.5  FPGA实现及仿真测试············································································································· 256

7.4  改进位同步技术的FPGA实现············································································································· 258

7.4.1  正交支路积分输出门限判决法································································································ 258

7.4.2  数字式滤波器法的工作原理···································································································· 260

7.4.3  随机徘徊滤波器的VHDL实现······························································································· 260

7.4.4  随机徘徊滤波器的仿真测试···································································································· 262

7.4.5  改进的数字滤波器工作原理···································································································· 263

7.4.6  改进滤波器的VHDL实现······································································································· 264

7.5  小结·························································································································································· 266

第8章  帧同步技术的FPGA实现············································································································· 267

8.1  异步传输与同步传输的概念·················································································································· 268

8.1.1  异步传输的概念························································································································ 268

8.1.2  同步传输的概念························································································································ 269

8.1.3  异步传输与同步传输的区别···································································································· 269

8.2  起止式同步的FPGA实现·········································································································· 270

8.2.1  RS-232串口通信协议··············································································································· 270

8.2.2  顶层模块的VHDL实现··········································································································· 272

8.2.3  时钟模块的VHDL实现··········································································································· 274

8.2.4  数据接收模块的VHDL实现··································································································· 276

8.2.5  数据发送模块的VHDL实现··································································································· 278

8.2.6  FPGA实现及仿真测试·········································································································· 280

8.3  帧同步码组及其检测原理········································································································· 283

8.3.1  帧同步码组的选择···················································································································· 283

8.3.2  间隔式插入法的检测原理········································································································ 284

8.3.3  连贯式插入法的检测原理········································································································ 285

8.3.4  帧同步的几种状态···················································································································· 286

8.4  连贯式插入法帧同步的FPGA实现····································································································· 287

8.4.1  实例要求及总体模块设计········································································································ 287

8.4.2  搜索模块的VHDL实现及仿真······························································································· 290

8.4.3  校核模块的VHDL实现及仿真······························································································· 293

8.4.4  同步模块的VHDL实现及仿真······························································································· 298

8.4.5  帧同步系统的FPGA实现及仿真···························································································· 303

8.5  小结······································································································································ 304

参考文献········································································································································ 305


 


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