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构建数字通信技术理论与实践之间的桥梁

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《数字通信同步技术的MATALB与FPGA实现_Altera/Veriog版》——目录  

2015-03-19 20:26:08|  分类: 通信同步技术 |  标签: |举报 |字号 订阅

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1  同步技术的概念及FPGA基础············································································· 1

1.1  数字通信中的同步技术

1.2  同步技术的实现方法

1.2.1  两种不同的实现原理

1.2.2  常用的工程实现途径

1.3  FPGA概念及其在信号处理中的应用

1.3.1  基本概念及发展历程

1.3.2  FPGA的结构和工作原理

1.3.3  FPGA在数字信号处理中的应用

1.4  Altera器件简介

1.5  Verilog HDL语言简介·

1.5.1  HDL语言简介

1.5.2  Verilog HDL语言特点

1.5.3  Verilog HDL程序结构

1.6  FPGA开发工具及设计流程

1.6.1  Quartus II开发套件

1.6.2  ModelSim仿真软件

1.6.3  FPGA设计流程·

1.7  MATLAB软件··

1.7.1  MATLAB软件介绍··

1.7.2  MATLAB工作界面

1.7.3  MATLAB的特点及优势·

1.7.4  MATLABQuartus的数据交互

1.8  小结

2  FPGA实现数字信号处理基础············································································ 35

2.1  FPGA中数的表示

2.1.1  莱布尼兹与二进制·

2.1.2  定点数表示·

2.1.3  浮点数表示

2.2  FPGA中数的运算··

2.2.1  /减法运算

2.2.2  乘法运算

2.2.3  除法运算

2.2.4  有效数据位的计算

2.3  有限字长效应

2.3.1  字长效应的产生因素

2.3.2  A/D转换器的字长效应·

2.3.3  系统运算中的字长效应

2.4  FPGA中的常用处理模块

2.4.1  加法器模块

2.4.2  乘法器模块

2.4.3  除法器模块

2.4.4  浮点运算模块

2.4.5  滤波器模块

2.5  小结

3  锁相技术原理及应用

3.1  锁相环的工作原理

3.1.1  锁相环路的模型

3.1.2  锁定与跟踪的概念

3.1.3  环路的基本性能要求

3.2  锁相环的组成

3.2.1  鉴相器

3.2.2  环路滤波器

3.2.3  压控振荡器

3.3  锁相环路的动态方程·

3.3.1  非线性相位模型

3.3.2  线性相位模型

3.3.3  环路的传递函数·

3.4  锁相环路的性能分析·

3.4.1  暂态信号响应

3.4.2  环路的频率响应

3.4.3  环路的稳定性

3.4.4  非线性跟踪性能

3.4.5  环路的捕获性能·

3.4.6  环路的噪声性能

3.5  锁相环路的应用

3.5.1  环路的两种跟踪状态

3.5.2  调频解调器·

3.5.3  调相解调器

3.5.4  调幅信号的相干解调·

3.5.5  锁相调频器

3.5.6  锁相调相器·

3.6  小结

4  载波同步的FPGA实现·

4.1  载波同步的原理

4.1.1  载波同步的概念及实现方法

4.1.2  锁相环的工作方式

4.2  锁相环路的数字化模型

4.2.1  数字鉴相器

4.2.2  数字环路滤波器

4.2.3  数字控制振荡器

4.2.4  数字环路的动态方程

4.3  输入信号建模与仿真·

4.3.1  工程实例需求

4.3.2  输入信号模型·

4.3.3  输入信号的MATLAB仿真·

4.4  载波同步环的参数设计

4.4.1  总体性能参数设计

4.4.2  数字鉴相器设计·

4.4.3  环路滤波器及数控振荡器设计

4.5  载波同步环的FPGA实现·

4.5.1  顶层模块的Verilog HDL实现

4.5.2  IIR低通滤波器的Verilog HDL实现

4.5.3  环路滤波器的Verilog HDL实现·

4.5.4  同步环路的FPGA实现·

4.6  载波同步环的仿真测试

4.6.1  测试激励的Verilog HDL设计·

4.6.2  单载波输入信号的仿真测试

4.6.3  调幅波输入信号的仿真测试··

4.6.4  关于载波环路参数的讨论

4.7  小结·

5  抑制载波同步的FPGA实现············································································· 133

5.1  抑制载波同步的原理························································································ 134

5.1.1  平方环工作原理························································································· 134

5.1.2  同相正交环工作原理··················································································· 135

5.1.3  判决反馈环工作原理··················································································· 136

5.2  输入信号建模与仿真························································································ 138

5.2.1  工程实例需求···························································································· 138

5.2.2  DPSK调制原理及信号特征·········································································· 138

5.2.3  DPSK信号传输模型及仿真·········································································· 139

5.3  平方环的FPGA实现························································································· 141

5.3.1  改进的平方环原理······················································································ 141

5.3.2  环路性能参数设计······················································································ 142

5.3.3  带通滤波器设计························································································· 143

5.3.4  顶层模块的Verilog HDL实现········································································ 145

5.3.5  带通滤波器的Verilog HDL实现····································································· 148

5.3.6  低通滤波器的Verilog HDL实现····································································· 152

5.3.7  FPGA实现后的仿真测试············································································· 154

5.4  同相正交环的FPGA实现·················································································· 156

5.4.1  环路性能参数设计······················································································ 156

5.4.2  低通滤波器Verilog HDL实现········································································ 157

5.4.3  其他模块的Verilog HDL实现········································································ 159

5.4.4  顶层模块的Verilog HDL实现········································································ 160

5.4.5  FPGA实现后的仿真测试············································································· 163

5.4.6  同相支路的判决及码型变换·········································································· 165

5.5  判决反馈环的FPGA实现·················································································· 167

5.5.1  环路性能参数设计······················································································ 167

5.5.2  顶层模块的Verilog HDL实现········································································ 168

5.5.3  积分判决模块的Verilog HDL实现·································································· 171

5.5.4  FPGA实现后的仿真测试············································································· 174

5.6  小结················································································································· 175

6  自动频率控制的FPGA实现············································································· 177

6.1  自动频率控制的概念························································································ 178

6.2  最大似然频偏估计的FPGA实现······································································· 179

6.2.1  最大似然频偏估计的原理·············································································· 179

6.2.2  最大似然频偏估计的MATLAB仿真······························································· 180

6.2.3  频偏估计的FPGA实现方法·········································································· 183

6.3  基于FFT载频估计的FPGA实现······································································· 185

6.3.1  离散傅里叶变换·························································································· 185

6.3.2  FFT算法原理及MATLAB仿真····································································· 187

6.3.3  FFT核的使用···························································································· 190

6.3.4  输入信号建模与MATLAB仿真····································································· 193

6.3.5  基于FFT载频估计的Verilog HDL实现···························································· 194

6.3.6  FPGA实现及仿真测试················································································· 198

6.4  FSK信号调制解调原理····················································································· 199

6.4.1  数字频率调制····························································································· 199

6.4.2  FSK信号的MATLAB仿真··········································································· 201

6.4.3  FSK相干解调原理······················································································ 204

6.4.4  AFC环解调FSK信号的原理········································································· 205

6.5  AFC环的FPGA实现························································································· 207

6.5.1  环路参数设计····························································································· 207

6.5.2  顶层模块的Verilog HDL实现········································································· 209

6.5.3  鉴频器模块的Verilog HDL实现······································································ 213

6.5.4  FPGA实现及仿真测试················································································· 214

6.6  小结················································································································· 215

7  位同步技术的FPGA实现················································································· 217

7.1  位同步的概念及实现方法·················································································· 218

7.1.1  位同步的概念····························································································· 218

7.1.2  滤波法提取位同步······················································································· 219

7.1.3  数字锁相环位同步法···················································································· 220

7.2  微分型位同步的FPGA实现·············································································· 222

7.2.1  微分型位同步的原理···················································································· 222

7.2.2  顶层模块的Verilog HDL实现········································································· 223

7.2.3  双相时钟信号的Verilog HDL实现··································································· 225

7.2.4  微分鉴相模块的Verilog HDL实现··································································· 227

7.2.5  单稳触发器的Verilog HDL实现······································································ 229

7.2.6  控制及分频模块的Verilog HDL实现································································ 231

7.2.7  位同步形成及移相模块的Verilog HDL实现······················································· 232

7.2.8  FPGA实现及仿真测试················································································· 234

7.3  积分型位同步的FPGA实现·············································································· 237

7.3.1  积分型位同步的原理···················································································· 237

7.3.2  顶层模块的Verilog HDL实现········································································· 239

7.3.3  积分模块的Verilog HDL实现········································································· 242

7.3.4  鉴相模块的Verilog HDL实现········································································· 243

7.3.5  FPGA实现及仿真测试················································································· 244

7.4  改进位同步技术的FPGA实现··········································································· 246

7.4.1  正交支路积分输出门限判决法········································································ 246

7.4.2  数字式滤波器法的工作原理··········································································· 248

7.4.3  随机徘徊滤波器的Verilog HDL实现································································ 249

7.4.4  随机徘徊滤波器的仿真测试··········································································· 250

7.4.5  改进的数字滤波器工作原理··········································································· 251

7.4.6  改进滤波器的Verilog HDL实现······································································ 252

7.5  小结················································································································· 254

8  帧同步技术的FPGA实现················································································· 255

8.1  异步传输与同步传输的概念·············································································· 256

8.1.1  异步传输的概念·························································································· 256

8.1.2  同步传输的概念·························································································· 257

8.1.3  异步传输与同步传输的区别··········································································· 257

8.2  起止式同步的FPGA实现·················································································· 258

8.2.1  RS-232串口通信协议··················································································· 258

8.2.2  顶层模块的Verilog HDL实现········································································· 260

8.2.3  时钟模块的Verilog HDL实现········································································· 262

8.2.4  数据接收模块的Verilog HDL实现··································································· 263

8.2.5  数据发送模块的Verilog HDL实现··································································· 266

8.2.6  FPGA实现及仿真测试················································································· 268

8.3  帧同步码组及其检测原理·················································································· 271

8.3.1  帧同步码组的选择······················································································· 271

8.3.2  间隔式插入法的检测原理·············································································· 272

8.3.3  连贯式插入法的检测原理·············································································· 273

8.3.4  帧同步的几种状态······················································································· 274

8.4  连贯式插入法帧同步的FPGA实现···································································· 275

8.4.1  实例要求及总体模块设计·············································································· 275

8.4.2  搜索模块的Verilog HDL实现及仿真································································ 277

8.4.3  校核模块的Verilog HDL实现及仿真································································ 281

8.4.4  同步模块的Verilog HDL实现及仿真································································ 286

8.4.5  帧同步系统的FPGA实现及仿真···································································· 291

8.5  小结················································································································· 292

参考文献························································································································ 293


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